![]() ![]() ADCLK954 clock buffer output waveforms with 3.3-V supply. Note that the characteristic impedance ( Z 0) of the trace will vary with trace dimension (length, width, and depth) the driver's output impedance must be matched to this characteristic impedance. When driving a DAC, the clock-distribution device should be placed as close as possible to the DAC's clock input so that the required high slew rate, high amplitude clock signals do not cause routing difficulties, generate EMI, or become degraded by dielectric and other losses. The ADCLK914 features a 7.5-GHz toggle rate. The ADCLK914 can drive 1.9 V high-voltage differential signals (HVDS) into 50-Ω loads for a total differential output swing of 3.8 V. The ADCLK954 comprises 12 output drivers that can drive 800-mV full-swing ECL (emitter-coupled logic) or LVPECL (low-voltage positive ECL) signals into 50-Ω loads for a total differential output swing of 1.6 V, as shown in Figure 2. Two such clock-distribution devices are the ADCLK954 2 clock fanout buffer and the ADCLK914 3 ultrafast clock buffer. To correctly implement a quality clock, use high-swing clock signals and short clock PCB traces place the device to be clocked as close to the clock-distribution device as possible. Higher frequency clock signals are subject to increased attenuation, distortion, and noise, but to improve jitter, which is worst at low slew rates (Figure 1), clock edges with a high slew rate are typically used. PCB traces behave like low-pass filters, attenuating clock signals as they travel along the trace and increasing pulse-edge distortion with trace length. When using clock distribution devices 1 or fanout buffers to clock ADCs and DACs, two main sources of signal degradation-printed-circuit board (PCB) trace implementation and output termination-need to be dealt with. ![]()
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